1. Field of the Invention
This invention relates to an instruction sequencer for use in a data processing systems which includes a plurality of functional units which are capable of being operated in parallel and more specifically to an instruction sequencer adapted for use in a data processing system having a plurality of functional units wherein the instruction sequencer programs parallel operations of the plurality of functional units in response to an instruction stream read out of a random access memory.
2. Description of the Prior Art
It is known in the art for a data processing system to execute an instruction using two or more functional units operating in parallel such as, for example, simultaneously executing a multiplication, addition, shift, or the like.
One well known, high-speed scientific digital computer which utilizes parallel processing in combination with a preprocessing stage and instruction reservation system is described in U.S. Pat. No. 3,346,851. Specifically, U.S. Pat. No. 3,346,851 discloses and teaches a digital computer central processor having a plurality of arithmetic or functional units and a scoreboard for instruction control which enables simultaneous execution of a plurality of instructions from a single program. In operation, the digital computer central processor disclosed in U.S. Pat. No. 3,346,851 includes means for controlling, in an orderly sequence, simultaneous operations of functional units in a high-speed digital computer wherein each functional unit is responsive to a specific instruction which is one of many instructions from a single program. This is accomplished by means of a reservation system which allows instructions to be issued to functional units for execution in the order prescribed by the programmed sequence. The control system allows the processing of instructions in parallel while maintaining instruction reservations which, in cooperation with the scoreboard, maintain a high degree of continuous simultaneous operation of all the functional units. The scoreboard permits the numerical operations and results from a specific functional unit to be reserved for use by the parallel functional unit upon completion of the operation of the functional unit which is to generate the numerical result reserved for a subsequent functional unit.
In the digital computer control processor of U.S. Pat. No. 3,346,851, different specific instructions are required for each functional unit and the control section cooperates with the scoreboard portion of the digital computer central processor to ultimately program the operation of the specific functional unit and utilizes the reservation system as the means for identifying a portion of the numerical data required for the numerical operation to be performed by that functional unit. This enables all functional units to operate at the highest possible efficiency for both deterministic and nondeterministic applications.
U.S. Pat. No. 3,234,523 discloses and teaches a program execution means for a stored program data processing system which utilizes discrete instruction words having a command portion which is divided into a plurality of sub-units designated as fields, each of which is capable of containing a value which controls a single operation such as a transfer, transfer with shift, add, subtract, or the like. Each of the fields is scanned during a different time phase of the execution. The instruction word contains a specific value for each field each field value is independent from one another enabling each field to be scanned at a different time. Also, U.S. Pat. No. 3,234,523 discloses the use of a decoder and command generator which is responsive to each field of the divided instruction word format to generate command signals for executing the operation specified by the single instruction word.
It is also known in the art to utilize parallel operation of functional units in high-speed specialized computers such as, for example, array processors or vector processors. Typical of such systems are those disclosed in U.S. Pat. Nos. 3,771,141; 4,287,566; and 4,051.551.
U.S. Pat. Nos. 4,287,566 and 3,771,141, wherein the inventor thereof is one of the coinventors herein, disclose the use of array processors wherein parallel operations in terms of arithmetic and data transfer operations are executed in parallel in clock cycles in response to a single instruction drawn from an instruction memory.
U.S. Pat. No. 4,287,566 discloses the use of an array processor for performing calculations utilizing data from two distinct two-dimensional arrays wherein the array processor incorporates multiplication, addition, subtraction, transfer and storage means. The arithmetic and storage operations and the two-dimensional array axis operations can be connected in parallel. Other known array processors operate in a similar manner as that described in U.S. Pat. No. 4,287,566.
U.S. Pat. No. 3,771,141 discloses and teaches an array processor wherein parallel operation of functional units is achieved as a consequence of implementing internal data registers and arithmetic circuits with multiple data inputs and by controlling the same in response to a particular instruction format. Specifically, instructions are stored in an instruction buffer and are drawn one at a time from a high-speed internal instruction memory which, in turn, is normally loaded, one instruction block at a time, from a core memory. The instruction format includes multiple fields which separately identify operands to be executed in parallel. In operation, instructions are read, one at a time, from an instruction pad which, in turn, is loaded from a large core memory. The instructions from the instruction pad include a plurality of fields of information. The control and timing units are responsive to the specific fields of the instruction and perform the operations in response to the specific instruction fields contained within the instruction word. When that instruction word operation has been completed, a new instruction word is then fetched from the instruction pad and the process is repeated. The array processor is capable of responding to specific fields within the single instruction word to provide parallel operations of two or more functional units in order to obtain the high processing speeds associated with data processors having parallel operations per instruction word.
U.S. Pat. No. 4,051,551 discloses a multidimension, parallel access computer memory system which includes a plurality of memory modules and a plurality of processors which are responsive to indexing tags which align a particular processor with a particular memory. The indexing tabs are generated at two different time frames and are operative to determine which data is to be read from a memory address and applied to a specific processor for processing. When the processing is completed, index tags are generated to return the processed data to a particular memory address. The parallel operation is achieved by matching various memory addresses and particular processors together with use of data buffering to interface data flow through multiplexes in order to obtain high processing speeds while permitting orderly processing and storage of data.
The concept of using an instruction stream having a plurality of instruction segments wherein blocks of the instruction stream are continually processed by an instruction sequencer to control on a continuous basis one, two or more functional units is not disclosed, suggested or taught by the known prior art.